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M82510 ASYNCHRONOUS SERIAL CONTROLLER
Military
Y
Asynchronous Operation 5- to 9-Bit Character Format Baud Rate DC to 288k Complete Error Detection Multiple Sampling Windows Two Independent Four-Byte Transmit and Receive FIFOs Programmable Threshold Two 16-bit Baud Rate Generators Timers System Clock Options On-Chip Crystal Oscillator External Clocks
Y Y Y Y Y Y
MCS -51 9-Bit Protocol Support Control Character Recognition CHMOS III with Power Down Mode Interrupts Maskable at Two Levels Auto Echo and Loopback Modes Seven I O Pins Dedicated and General Purpose Available in 28-Lead CERDIP and 28-Pad LCC Packages Military Temperature Range b 55 C to a 125 C (TC)
Y Y
Y
Y
Y
Y
The Intel CHMOS M82510 is designed to increase system efficiency in asynchronous environments such as modems serial ports including expanding performance areas MCS -51 9-bit format and high speed async The functional support provided in the M82510 is unparalleled 2 baud rate generators timers provide independent data rates or protocol timeouts a crystal oscillator and smart modem I O simplify system logic New features dual FIFOs and Control Character Recognition (CCR) dramatically reduce CPU interrupts and increase software efficiency The M82510's software versatility allows emulation of the INS 8250A 16450 for IBM PC AT compatibility or a high performance mode configured by 35 control registers All interrupts are maskable at 2 levels The multi-personality I O pins are configurable as desired A DPLL and multiple sampling of serial data improve data reliability for high speed asynchronous communication The compact 28-pin M82510 is fabricated in CHMOS III technology and includes a software powerdown option
IBM and PC AT are registered trademarks of IBM Corporation
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Figure 1 Block Diagram
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1996
March 1996
Order Number 271072-007
M82510
28-Pad LCC
28-Pin Cerdip
271072 - 2 271072 - 55
Figure 2 Package Pinouts
M82510 PINOUT DEFINITION
Symbol RESET CS A2-A0 D7-D0 RD WR INT Pin No 17 18 2422 4 25 20 19 5 Type I I I IO I I O Name and Description RESET A high on this input pin resets the M82510 to the Default Wake-up mode CHIP SELECT A low on this input pin enables the M82510 and allows read or write operations ADDRESS PINS These inputs interface with three bits of the System Address Bus to select one of the internal registers for read or write DATA BUS Bidirectional three state eight-bit Data Bus These pins allow transfer of bytes between the CPU and the M82510 READ A low on this input pin allows the CPU to read Data or Status bytes from the M82510 WRITE A low on this input allows the CPU to write Data or Control bytes to the M82510 INTERRUPT A high on this output pin signals an interrupt request to the CPU The CPU may determine the particular source and cause of the interrupt by reading the M82510 Status registers MULTIFUNCTION This input pin serves as a source for the internal system clock The clock may be asynchronous to the serial clocks and to the processor clock This pin may be used in one of two modes CLK in this mode an externally generated TTL compatible clock should be used to drive this input pin X1 in this mode the clock is internally generated by an on-chip crystal oscillator This mode requires a crystal to be connected between this pin (X1) and the X2 pin (See System Clock Generation ) MULTIFUNCTION This is a dual function pin which may be configured to one of a general purpose output pin controlled by the the following functions OUT2 CPU only available when CLK X1 pin is driven by an externally generated clock X2 - this pin serves as an output pin for the crystal oscillator Note The configuration of the pin is done only during hardware reset For more details refer to the System Clock Generation
CLK X1
9
I
OUT2 X2
8
O
Pins 28 -25 and Pins 4-1
2
M82510
M82510 PINOUT DEFINITION (Continued)
Symbol TXD RXD RI SCLK Pin No 6 13 10 Type O I I Name and Description TRANSMIT DATA Serial data is transmitted via this output pin starting at the Least Significant bit RECEIVE DATA Serial data is received on this input pin starting at the Least Significant bit MULTIFUNCTION This is a dual function pin which can be configured to one of the following functions RI - Ring Indicator - Input active low This is a general purpose input pin accessible by the CPU SCLK - This input pin may serve as a source for the internal serial clock(s) RxClk and or TxClk See Figure 12 BRG sources and outputs MULTIFUNCTION This is a dual function pin which may be configured to one of the following functions DTR - Data Terminal Ready Output active low This is a general purpose output pin controlled by the CPU TB - This pin outputs the BRGB output signal when configured as either a clock generator or as a timer When BRGB is configured as a timer this pin outputs a ``timer expired pulse '' When BRGB is configured as a clock generator it outputs the BRGB output clock MULTIFUNCTION This is a multifunction pin which may be configured to one of the following functions DSR - Data Set Ready Input active low This is a general purpose input pin accessible by the CPU TA - This pin is similar in function to pin TB except it outputs the signals from BRGA instead of BRGB OUT0 - Output pin This is a general purpose output pin controlled by the CPU REQUEST TO SEND Output pin active low This is a general purpose output pin controlled by the CPU In addition in automatic transmission mode this pin along with CTS controls the transmission of data (See Transmit modes for further detail ) During hardware reset this pin is an input It is used to determine the System Clock Mode (See System Clock Generation for further detail ) CLEAR TO SEND Input pin active low In automatic transmission mode it directly controls the Transmit Machine (See transmission mode for further details ) This pin can be used as a General Purpose Input MULTIFUNCTION This is a multifunction pin which may be configured to one of the following functions DCD - Data Carrier Detected Input pin active low This is a general purpose input pin accessible by the CPU ICLK - This pin is the output of the internal system clock OUT1 - General purpose output pin Controlled by the CPU Ground Power a 5V Supply Table 1 Multifunction Pins Pin 8 9 10 11 12 14 15 16
Default
DTR TB
15
O
DSR TA OUT0
11
IO
RTS
16
O
CTS
14
I
DCD ICLK OUT1
12
IO
VSS VCC
7 21
P P
IO OUT2
Timing X2 CLK X1 SCLK
Modem
RI DSR DCD CTS
OUT0 OUT1
TA ICLK
TB
DTR RTS 3
M82510
Its register set can be used in 8250A 16450 compatibility or High Performance modes The 8250A 16450 mode is the default wake-up mode in which only the 8250A 16450 compatible registers are accessible The remaining registers are default configured to support 8250A 16450 emulation
GENERAL DESCRIPTION
The M82510 can be functionally divided into seven major blocks (See Fig 1) Bus Interface Unit Timing Unit Modem Module Tx FIFO Rx FIFO Tx Machine and Rx Machine Six of these blocks (all except Bus Interface Unit) can generate block interrupts Three of these blocks can generate secondlevel interrupts which reflect errors status within the block (Receive Machine Timing Unit and the Modem Module) The Bus interface unit allows the M82510 to interface with the rest of the system It controls access to device registers as well as generation of interrupts to the external world The FIFOs buffer the CPU from the Serial Machines and reduce the interrupt overhead normally required for serial operations The threshold (level of occupancy in the FIFO which will generate an interrupt) is programmable for each FIFO The timing unit controls generation of the system clock through either its on-chip crystal oscillator or an externally generated clock It also provides two Baud Rate Generators Timers with various options and modes to support serial communication
Software Interface
FUNCTIONAL DESCRIPTION CPU Interface
The M82510 has a simple demultiplexed Bus Interface which consists of a bidirectional three-state eight-bit data bus and a three-bit address bus An Interrupt pin along with the Read Write and Chip Select are the remaining signals used to interface with the CPU The three address lines along with the Bank Pointer register are used to select the registers The M82510 is designed to interface to all Intel microprocessor and microcontroller families Like most other I O based peripherals it is programmed through its registers to support a variety of functions
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Figure 3 M82510 Register Architecture The M82510 is configured and controlled through its 35 registers which are divided into four banks Only one bank is accessible at any one time The bank switching is done by changing the contents of the bank pointer (GIR BANK - BANK0 BANK1) The banks are logically grouped into 8250A 16450 compatible (0) General Work Bank (1) General Configuration (2) and Modem Configuration (3) The 8250A 16450 compatible bank (Bank 0) is the default bank upon power up The M82510 registers can be categorized under the following
Table 2 M82510 Register Block Functions Status FIFO MODEM RX TX TIMER DEVICE 8250 FLR MSR RST RXF LSR TMST GSR GIR LSR MSR GIR Enable MIE RIE LSR TMIE GER GER Configuration FMD PMD RMD TMD CLCF BACF BBCF IMD LCR MCR Command MCR RCM TCM TMCR ICM MCR RXD TXD BBL BAL RXF TXF BBH BAH Data
TXD RXD BAL BAH
4
M82510
8250 Compatibility
Upon power up or reset the M82510 comes up in the default wake up mode The 8250A 16450 compatible bank bank zero is the accessible bank and all the other registers are configured via their default values to support this mode Table 3 8250A 16450 Compatible Registers M82510 Registers (Bank 0) Address 00 (DLAB e 0) 01 (DLAB e 0) 00 (DLAB e 1) 01 (DLAB e 1) 02 03 04 05 06 07 Read RxD GER BAL BAH GIR BANK LCR MCR LSR MSR ACR0 Write TxD GER BAL BAH BANK LCR MCR LSR MSR ACR0 8250A Registers Read RBR IER DLL DLM IIR LCR MCR LSR MSR SCR LCR MCR LSR MSR SCR Write THR IER DLL DLM
Table 4 Default Wake-Up Mode RxD TxD BAL BAH GER GIR BANK LCR MCR LSR MSR ACR0 RST 02H 00H 00H 01H 00H 00H 60H 00H 00H 00H ACR1 RIE RMD CLCF BACF BBCF PMD MIE TMIE BBL BBH 00H 1EH 00H 00H 04H 84H FCH 0FH 00H 05H 00H RxF TxF TMST TMCR FLR RCM TCM GSR ICM FMD TMD IMD 00H 00H 0CH 12H 00H 30H
5
M82510
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Figure 4 Interrupt Structure
Interrupts
There are two levels of interrupt status reporting within the M82510 The first level is the block level interrupts such as RX FIFO Tx FIFO Rx Machine Tx Machine Timing unit and Modem Module The status of these blocks is reported in the General Status and General Interrupt Registers The second level is the various sources within each block only three of the blocks generate second level interrupts (Rx Machine Timing Unit and Modem Module) Interrupt requests are maskable at both the block level and at the individual source level within the module If more than one unmasked block requests interrupt service an on-chip interrupt controller will resolve contention on a priority basis (each block has a fixed priority) An interrupt request from a particular block is activated if one of the unmasked status bits within the status register for the block is set A CPU service operation e g reading the appropriate status register will reset the status bits ACKNOWLEDGE MODES The interrupt logic will assert the INT pin when an interrupt is coded into the General Interrupt register The INT pin is forced low upon acknowledgment The M82510 has two modes of interrupt acknowledgment 1 Manual Acknowledge
The CPU must issue an explicit Interrupt Acknowledge command via the Interrupt Acknowledge bit of the Internal Command register As a result the INT pin is forced low for two clocks and then updated 2 Automatic Acknowledge As opposed to the Manual Acknowledge mode when the CPU must issue an explicit interrupt acknowledge command an interrupt service operation is considered as an automatic acknowledgment This forces the INT pin low for two clock cycles After two cycles the INT pin is updated i e if there is still an active non-masked interrupt request the INT pin is set HIGH INTERRUPT SERVICE A service operation is an operation performed by the CPU which causes the source of the M82510 interrupt to be reset (it will reset the particular status bit causing the interrupt) An interrupt request within the M82510 will not reset until the interrupt source has been serviced Each source can be serviced in two or three different ways one general way is to disable the particular status bit causing the interrupt via the corresponding block enable register Setting the appropriate bit of the enable register to zero will mask off the corresponding bit in the status register thus causing an edge on the input line to the interrupt logic The same effect can be achieved by masking
6
M82510
off the particular block interrupt request in GSR via the General Enable Register Another method which is applicable to all sources is to issue the Status Clear command from the Internal Command Register The detailed service requirements for each source are given below Table 5 Service Procedures Interrupt Status Bits Interrupt Source Registers Masking Timers Specific Service The M82510 has an on-chip oscillator to generate its system clock The oscillator will take the inputs from a crystal attached to the X1 and X2 pins This mode is configured via a hardware strapping option on RTS
TMST (1- 0) TMIE (1-0) Read TMST GSR (5) GER (5) GER (4) RIE (7-1) GER (2) Write Character to tX FIFO Read RST or LSR Write 0 to bit in RST LSR Write 0 to LSR RST Bit zero Read Character Write to FIFO Read GIR(1) Read MSR write 0 into the appropriate bits of MSR (3- 0)
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Tx GSR (4) Machine LSR (6) Rx LSR (4- 1) Machine RST (7- 1) GSR (2)
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Figure 6 Strapping Option During hardware reset the RTS pin is an input it is weakly pulled high from within and then checked If it is driven low externally then the M82510 is configured for the Crystal Oscillator otherwise an external clock is expected EXTERNALLY GENERATED SYSTEM CLOCK
Rx FIFO RST LSR (0) GER (0) GSR (0)
Tx FIFO LSR (5) GSR (1) Modem MSR (3-0) GSR (3)
GER (1) MIE (3-0) GER (3)
NOTE 1 Only if pending interrupt is Tx FIFO
Figure 7 External Clock This is the default configuration Under normal conditions the system clock is divided by two however the user may disable divide by two via a hardware strapping option on the DTR pin The Hardware strapping option is similar to the one used on the RTS pin It is forbidden to strap both DTR and RTS
System Clock Generation
The M82510 has two modes of System Clock Operation It can accept an externally generated clock or it can use a crystal to internally generate its system clock CRYSTAL OSCILLATOR
Transmit
The two major blocks involved in transmission are the Transmit FIFO and the Transmit Machine The Tx FIFO acts as a buffer between the CPU and the Tx Machine Whenever a data character is written to the Transmit Data register it along with the Transmit Flags (if applicable) is loaded into the Tx FIFO
Parallel Resonant Crystal
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Figure 5 Crystal Oscillator
7
M82510
TX FIFO
TRANSMIT CLOCKS There are two modes of transmission clocking 1X and 16X In the 1X mode the transmitted data is synchronous to the transmit clock as supplied by the SCLK pin In this mode stop-bit length is restricted to one or two bits only In the 16X mode the data is not required to be synchronous to the clock (Note The Tx clock can be generated by the BRGs or from the SCLK pin ) MODEM HANDSHAKING The transmitter has three modes of handshaking Manual Mode In this mode the CTS and RTS pins are not used by the Tx Machine (transmission is started regardless of the CTS state and RTS is not forced low) The CPU may manage the handshake itself by accessing the CTS and RTS signals through the MODEM CONTROL and MODEM STATUS registers Semi-Automatic Mode In this mode the RTS pin is activated whenever the transmitter is enabled The CTS pin's state controls transmission Transmission is enabled only if CTS is active If CTS becomes inactive during transmission the Tx Machine will complete transmission of the current character and then go to the inactive state until CTS becomes active again Automatic Mode This mode is similar to the semiautomatic mode except that RTS will be activated as long as the transmitter is enabled and there are more characters to transmit The CPU need only fill the FIFO the handshake is done by the Tx Machine When both the shift register and the FIFO are empty RTS automatically goes inactive (Note The RTS pin can be forced to the active state by the CPU regardless of the handshaking mode via the MODEM CONTROL register )
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Figure 8 Tx FIFO The Tx FIFO can hold up to four eleven-bit characters (nine-bits data parity and address flag) It has separate read and write mechanisms The read and write pointers are incremented after every operation to allow data transfer to occur in a First In First Out fashion The Tx FIFO will generate a maskable interrupt when the level in the FIFO is below or equal to the Threshold The threshold is user programmable For example if the threshold equals two and the number of characters in the Tx FIFO decreases from three to two the FIFO will generate an interrupt The threshold should be selected with regard to the system's interrupt service latency NOTE There is a one character transmission delay between FIFO empty and Transmitter Idle so a threshold of zero may be selected without getting an underrun condition Also if more than four characters are written to the FIFO an overrun will occur and the extra character will not be written to the Tx FIFO This error will not be reported to the CPU TX MACHINE The Tx Machine reads characters from the Tx FIFO serializes the bits and transmits them over the TXD pin according to the timing signals provided for transmission It will also generate parity transmit break (upon CPU request) and manage the modem handshaking signals (CTS and RTS) if configured so The Tx machine can be enabled or disabled through the Transmit Command register or CTS If the transmitter is disabled in the middle of a character transmission the transmission will continue until the end of the character only then will it enter the disable state 8
Receive
The M82510 reception mechanism involves two major blocks the Rx Machine and the Rx FIFO The Rx Machine will assemble the incoming character and its associated flags and then LOAD them on to the Rx FIFO The top of the FIFO may be read by reading the Receive Data register and the Receive Flags Register The receive operation can be done in two modes In the normal mode the characters are received in the standard Asynchronous format and only control characters are recognized In the ulan mode the nine bit protocol of the MCS-51 family is supported and the ulan Address characters rather than Control Characters are recognized
M82510
Manual Mode In this mode the Rx Machine does not control the FIFO automatically however the user may UNLOCK LOCK the FIFO by using the RECEIVE COMMAND register RX MACHINE The RX Machine has two modes of clocking the incoming data 16X or 1X In 16X synchronization is done internally in the 1X mode the data must be synchronous to the SCLK pin input The Rx Machine synchronizes the data passes it through a digital filter to filter out the spikes and then uses the voting counter to generate the data bit (multiple sampling of input RXD) Bit polarity decisions are made on the basis of majority voting i e if the majority of the samples are ``1'' the result is a ``1'' bit If all samples are not in agreement then the bit is also reported as a noisy bit in the RECEIVE FLAGS register The sampling window is programmable for either 3 16 or 7 16 samples The 3 16 mode is useful for high frequency transmissions or when serious RC delays are expected on the channel The 7 16 is best suited for noisy media The Rx machine also has a DPLL to overcome frequency shift problems however using it in a very noisy environment may increase the error so the user can disable the DPLL via the Receive Mode register The Rx Machine will generate the parity and the address marker as well as any framing error indications Start Bit Detection The falling edge of the Start bit resets the DPLL counter and the Rx Machine starts sampling the input line (the number of samples is determined by the configuration of the sampling window mode) The Start bit verification can be done through either a majority voting system or an absolute voting system The absolute voting requires that all the samples be in agreement If one of the samples does not agree then a false Start bit is determined and the Rx Machine returns to the Start Bit search Mode Once a Start bit is detected the Rx Machine will use the majority voting sampling window to receive the data bits Break Detection If the input is low for the entire character frame including the stop Bit then the Rx Machine will set Break Detected as well as Framing Error in the RECEIVE STATUS and LINE STATUS registers It will push a NULL character onto the Rx FIFO with a framing-error and Break flag (As part of the Receive Flags) The Rx Machine then enters the Idle state When it sees a mark it will set Break Terminated in RECEIVE STATUS and LINE STATUS registers and resume normal operation
RX FIFO
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Figure 9 Rx FIFO The Rx FIFO is very similar in structure and basic operation to the Tx FIFO It will generate a maskable interrupt when the FIFO level is above the threshold The Rx FIFO can also be configured to operate as a one-byte buffer This mode is used for 8250 compatible software drivers An overrun will occur when the FIFO is full and the Rx Machine has a new character for the FIFO In this situation the oldest character is discarded and the new character is loaded from the Rx Machine An Overrun error bit will also be set in the RECEIVE STATUS and LINE STATUS registers The user has the option to disable the loading of incoming characters on to the Rx FIFO by using the UNLOCK LOCK FIFO commands (See RECEIVE COMMAND register ) When the Rx FIFO is locked it will ignore load requests from the Rx Machine and thus the received characters will not be loaded into the FIFO and may be lost (if another character is received) These two commands are useful when the CPU is not willing to receive characters or is waiting for specific Control Address characters In uLAN mode there are three options of address recognition each of these options varies in the amount of CPU offload and degree of FIFO control through OPEN LOCK FIFO commands Automatic Mode In this mode the Rx Machine will open the FIFO whenever an Address Match occurs it will LOCK the FIFO if an address mismatch occurs Semi-Automatic Mode In this mode the Rx Machine will open the FIFO whenever an address character is received It will not lock the FIFO if the Address does not match The user is responsible for locking the Rx FIFO
9
M82510
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Figure 10 Sampling Windows Control Characters The Rx machine can generate a maskable interrupt upon reception of standard ASCII or EBCDIC control characters or an Address marker is received in the uLAN mode The Rx machine can also generate a maskable interrupt upon a match with programmed characters in the Address Control Character 0 or Address Control Character 1 registers Table 6 Control Character Recognition CONTROL CHARACTER RECOGNITION A STANDARD SET X ASCII 000X XXXX a 0111 1111 (ASCII DEL) (00 - 1FH a 7 FH) OR
X
SCLK SYS CLK XTAL CLK BRGA OUTPUT SOFTWARE CONTROLLED GATE SOURCE -BOUT Rx CLK Tx CLK
optionally output to external devices via the TA TB pins (see Figure 11 BRG Sources and Outputs)
SOFTWARE CONTROLLED GATE SYS CLK XTAL CLK SCLK SOURCE -AOUT Rx CLK Tx CLK BRGB SOURCE
Figure 11 BRG Sources and Outputs 00XX XXXX (00 - 3FH)
EBCDIC
BAUD RATE GENERATION The Baud Rate is generated by dividing the source clock with the divisor count (from the Divisor count registers) The count is loaded from the divisor count registers into a count down register A 50% duty cycle is generated by counting down in steps of two When the count is down to 2 the entire count is reloaded and the output clock is toggled Optionally the two BRGs may be cascaded to provide a larger divisor
f0 e fin Divisor
B
User Programmed X ACR0 ACR1 XXXX XXXX REGISTERS
Baud-Rate Generators Timers
The M82510 has two-on-chip 16-bit baud-rate generators Each BRG can also be configured as a Timer and is completely independent of the other This can be used when the Transmit and Receive baud rates are different The mode the output and the source of each BRG is configurable and can also be
where f in is the input clock frequency and Divisor is the count loaded into the appropriate count registers
10
M82510
To start counting the Timer has to be triggered via the Start Timer Command To restart the Timer after terminal count or while counting the software has to issue the trigger command again While counting the Timer can be enabled or disabled by using a software controlled Gate It is also possible to output a pulse generated upon terminal count through the TA or TB pins In 1X clock mode the only clock source available is the SCLK pin The serial machines (both Tx Machine and Rx Machine) can independently use one of two clock modes either 1X or 16X Also no configuration changes are allowed during operation as each write in the BRG configuration registers causes a reset signal to be sent to the BRG logic The mode or source clocks may be changed only after a Hardware or Software reset The Divisor (or count depending upon the mode) may be updated during operation unless the particular BRG machine is being used as a clock source for one of the serial machines and the particular serial machine is in operation at the time Loading the count registers with ``0'' is forbidden in all cases and loading it with a ``1'' is forbidden in the Timer Mode only SERIAL DIAGNOSTICS The M82510 supports two modes of Loopback operation Local Loopback and Remote Loopback as well as an Echo mode for diagnostics and improved throughput LOCAL LOOPBACK
Table 7 Standard Baud Rates Bit Rate 110 300 1200 2400 9600 19 200 38 400 56 000 288 000 16x Divisor 5236 (1474h) 1 920 (780h) 480 (1E0h) 240 (F0h) 60 (3Ch) 30 (1Eh) 15 (0Fh) 10 (0Ah) 2 (02h) 2 8% % Error 007%
Source CLK e Internal Sys Clk e 18 432 MHz 2 e 9 216 MHz
The BRG counts down in increments of two and then is divided by two to generate a 50% duty cycle however for odd divisors it will count down the first time by one All subsequent countdowns will then continue in steps of two In those cases the duty cycle is no longer exactly 50% The deviation is given by the following equation
deviation e 1 (2 X divisor)
The BRG can operate with any divisor between 1 and 65 535 however for divisors between 1 and 3 the duty cycle is as follows Table 8 Duty Cycles Divisor 3 2 1 0 Duty Cycle 33% 50% Same as Source FORBIDDEN
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Figure 12 Local Loopback The Tx Machine output and Rx Machine input are shorted internally TXD pin output is held at Mark This feature allows simulation of Transmission Reception of characters and checks the Tx FIFO Tx Machine Rx Machine and Rx FIFO along with the software without any external side effects The modem outputs OUT1 OUT2 DTR and RTS are internally shorted to RI DCD DSR and CTS respectively OUT0 is held at a mark state
Timer Mode
Each of the M82510 BRGs can be used as Timers The Timer is used to generate time delays by counting the internal system clock When enabled the Timer uses the count from the Divisor Count registers to count down to 1 Upon terminal count a maskable Timer Expired interrupt is generated The delay between the trigger and the terminal count is given by the following equation
Delay e Count X (System Clock Period)
11
M82510
The M82510 powers down when the power down command is issued via the Internal Command Register (ICM) There are two modes of power down Sleep and Idle In Sleep mode even the system clock of the M82510 is shut down The system clock source of the M82510 can either be the Crystal Oscillator or an external clock source If the Crystal Oscillator is being used and the power down command is issued then the M82510 will automatically enter the Sleep mode If an external clock is being used then the user must disable the external clock in addition to issuing the Power Down command to enter the Sleep mode The benefit of this mode is the increased savings in power consumption (typical power consumption in the Sleep mode is in the ranges of 100s of microAmps) However upon wake up the user must reprogram the device To exit this mode the user can either issue a Hardware reset or read the FIFO Level Register (FLR) and then issue a software reset In either case the contents of the M82510 registers are not preserved and the device must be reprogrammed prior to operation If the Crystal Oscillator is being used then the user must allow enough time for the oscillator to wake up before issuing the software reset The M82510 is in the idle mode when the Power Down command is issued and the system clock is still running (i e the system clock is generated externally and not disabled by the user) In this mode the contents of all registers and memory cells are preserved however the power consumption in this mode is greater than in the Sleep mode Reading FLR will take the M82510 out of this mode NOTE The data read from FLR when exiting Power Down is invalid and should be ignored
REMOTE LOOPBACK
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Figure 13 Remote Loopback The TXD pin and RXD pin are shorted internally (the data is not sent on to the RX Machine) This feature allows the user to check the communications channel as well as the Tx and Rx pin circuits not checked in the Local Loopback mode AUTO ECHO
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Figure 14 Auto Echo In Echo Mode the received characters are automatically transmitted back When the characters are read from the Rx FIFO they are automatically pushed back onto the Tx FIFO (the flags are also included) The Rx Machine baud rate must be equal to or less than the Tx Machine baud rate or some of the characters may be lost The user has an option of preventing echo of special characters Control Characters and characters with Errors
Power Down Mode
The M82510 has a ``power down'' mode to reduce power consumption when the device is not in use
12
M82510
DETAILED REGISTER DESCRIPTION
Table 9 Register Map Bank 0 (NAS) 8250A 16450 Address 0 (DLAB 1 (DLAB 0 (DLAB 1 (DLAB 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 (DLAB 1 (DLAB 0 (DLAB 1 (DLAB 2 3 4 5 6 7
e e e e e e e e
Read Register 0) 0) 1) 1) RXD GER BAL BAH GIR BANK LCR MCR LSR MSR ACR0 RXD RXF GIR BANK TMST FLR RST MSR GSR FMD GIR BANK TMD IMD ACR1 RIE RMD 0) 0) 1) 1) CLCF BACF BBL BBH GIR BANK BBCF PMD MIE TMIE
Write Register TXD GER BAL BAH BANK LCR MCR LSR MSR ACR0 TXD TXF BANK TMCR MCR RCM TCM ICM FMD BANK TMD IMD ACR1 RIE RMD CLCF BACF BBL BBH BANK BBCF PMD MIE TMIE
1 (WORK)
2 (GENERAL CONF)
3 (MODEM CONF)
(1) ACRO is used in INS8250 as a Scratch-Pad Register (2) DLAB e LCR Bit 7 The M82510 has thirty-five registers which are divided into four banks of register banks Only one bank is accessible at any one time The bank is selected through the BANK1-0 bits in the GIR BANK register The individual registers within a bank are selected by the three address lines (A2 - 0) The M82510 registers can be grouped into the following categories
13
M82510
BANK ZERO 8250A 16450 COMPATIBLE BANK Register TxD (33) RxD (35) BAL (11) BAH (12) GER (16) 0 0 Timer Interrupt Enable 7 Tx Data bit 7 Rx Data bit 7 6 5 4 Tx Data bit 4 Rx Data bit 4 3 Tx Data bit 3 Rx Data bit 3 2 Tx Data bit 2 Rx Data bit 2 1 Tx Data bit 1 Rx Data bit 1 0 Tx Data bit 0 Rx Data bit 0 Address Default 0 0 0 1 Tx FIFO Interrupt Enable Active Block Int bit 0 Character Length bit 1 Rx FIFO Interrupt Enable Interrupt Pending Character Length bit 0 1 02H 00H 00H
Tx Data Tx Data bit 6 bit 5 Rx Data Rx Data bit 6 bit 5
BRGA LSB Divide Count (DLAB e 1) BRGA MSB Divide Count (DLAB e 1) Tx Machine Modem Interrupt Interrupt Enable Enable 0 Active Block Int bit 2 Parity Mode bit 0 Rx Machine Interrupt Enable Active Block Int bit 1 Stop bit Length bit 0
GIR BANK (21) LCR (2)
0
BANK BANK Pointer Pointer bit 1 bit 0 Parity Mode bit 2
2
01H
DLAB Set Divisor Break Latch Access bit 0 0 0 TxM Idle
Parity Mode bit 1
3
00H
MCR (32) LSR (22) MSR (27)
OUT 0 Loopback OUT 2 OUT 1 Complement Control bit Complement Complement Tx FIFO Interrupt Break Detected Framing Error Parity Error
RTS DTR Complement Complement Overrun Error Rx FIFO Int Req State Change in CTS
4 5 6
00H 60H 00H
DCD Input RI Input DSR Input Inverted Inverted Inverted
CTS Input State Inverted Change in DCD
State (HxL) State Change Change in RI in DSR
ACR0 (5)
Address or Control Character Zero BANK ONE GENERAL WORK BANK
7
00H
Register TxD (33) RxD (35) RxF (24)
7 Tx Data bit 7 Rx Data bit 7
6
5
4 Tx Data bit 4 Rx Data bit 4 Rx Char Parity Error 0 0
3 Tx Data bit 3 Rx Data bit 3 Address or Control Character 0 Active Block Int bit 2
2 Tx Data bit 2 Rx Data bit 2 Break Flag 0 Active Block Int bit 1
1 Tx Data bit 1 Rx Data bit 1 Rx Char Framing Error 0 Active Block Int bit 0 Timer B Expired
0 Tx Data bit 0 Rx Data bit 0 Ninth Data bit of Rx Char 0 Interrupt Pending Timer A Expired Start Timer A
Address Default 0 0 1
Tx Data Tx Data bit 6 bit 5 Rx Data Rx Data bit 6 bit 5 Rx Char Rx Char OK Noisy
TxF (34) GIR BANK (21) TMST (26) TMCR (31) MCR (32)
Address Software Ninth bit Marker bit Parity bit of Data Char 0 BANK Pointer bit 1 BANK Pointer bit 0 Gate B State 0 0 0 0 Trigger Gate B
1 2 01H
Gate A State Trigger Gate A 0 0
3 3 4
30H
Start Timer B
OUT 0 Loopback OUT 2 OUT 1 RTS DTR Complement Control bit Complement Complement Complement Complement
00H
NOTE The register number is provided as a reference number for the register description
14
M82510
BANK ONE Register FLR (25) RST (23) Address Control Character Received RCM (30) Rx Enable 7 6 5 Rx FIFO Level
GENERAL WORK BANK (Continued) 4 3 2 1 Tx FIFO Level Parity Error Overrun Rx FIFO Error Interrupt Requested 0 0 0 Address Default 4 5 00H 00H
Address Break Break Framing Control Terminated Detected Error Character Match Rx Disable Flush RxM DSR Input Inverted 0 Timer Interrupt Flush Rx FIFO Lock Rx FIFO
Open Rx FIFO
5 6 00H
MSR (27) DCD RI Input Complement Inverted TCM (29) GSR (20) ICM (28) 0 0 0 0
CTS Input State Inverted Change in DCD 0 TxM Interrupt Flush Tx Machine Modem Interrupt
State State State Change Change Change in RI in DSR in CTS Flush Tx Tx FIFO Enable Tx Disable
6 7 7 12H
RxM Tx FIFO Rx FIFO Interrupt Interrupt Interrupt Power Down Mode 0
0
Software Manual Int Status Reset Acknowledge Clear Command
BANK TWO Register FMD (4) GIR BANK (21) TMD (3) 7 0 0 6 0 BANK Pointer bit 1 5
GENERAL CONFIGURATION 4 3 0 Active Block Int bit 2 2 0 1 0 Address Default 1 2 00H 01H
Rx FIFO Threshold BANK Pointer bit 0 0
Tx FIFO Threshold
Active Active Interrupt Block Int Block Int Pending bit 1 bit 0 Software Parity Mode Stop Bit Length
Error Echo Disable 0
Control 9-bit Character Character Echo Disable Length 0 0
Transmit Mode
3
00H
IMD (1)
0
Interrupt Rx FIFO ulan Acknowledge Depth Mode Mode Select Framing Error Interrupt Enable Parity Error Interrupt Enable Overrun Error Interrupt Enable
Loopback or Echo Mode of Operation 0
4
0CH
ACR1 (6) RIE (17) Address Control Character Recognition Interrupt Enable Address Control Character Match Interrupt Enable
Address or Control Character 1 Break Terminate Interrupt Enable Break Detect Interrupt Enable
5 6
00H 1EH
RMD (7)
Address Control Character Mode
Disable DPLL
Sampling Start bit Window Sampling Mode Mode
0
0
0
7
00H
BANK THREE Register CLCF (8) BACF (9) 7 Rx Clock Mode 0 6 Rx Clock Source BRGA Clock Source 5 Tx Clock Mode 0
MODEM CONFIGURATION 4 Tx Clock Source 0 3 0 0 2 0 BRGA Mode 1 0 0 0 0 0 Address 0 1 Default 00H 04H
BBL (13) BBH (14)
BRGB LSB Divide Count (DLAB e 1) BRGB MSB Divide Count (DLAB e 1)
0 1
05H 00H
15
M82510
BANK THREE Register GIR BANK (21) BBCF (10) PMD (15) 7 0 6 BANK Pointer bit 1 5 BANK Pointer bit 0 0
MODEM CONFIGURATION (Continued) 4 0 3 Active Block Int bit 2 0 2 Active Block Int bit 1 BRGB Mode DTR TB Function 1 Active Block Int bit 0 0 0 0 Interrupt Pending 0 0 Address Default 2 01H
BRGB Clock Source
0
3 4
84H FCH
DCD ICLK DCD ICLK DSR TA DSR TA RI SCLK OUT 1 OUT 1 OUT 0 OUT 0 Function Direction Function Direction Function 0 0 0 0
MIE (19)
DCD State RI State DSR State CTS State Change Int Change Int Change Int Change Int Enable Enable Enable Enable 0 0 Timer B Interrupt Enable Timer A Interrupt Enable
5
0FH
TMIE (18)
0
0
0
0
6
00H
CONFIGURATION
These read write registers are used to configure the device They may be read at anytime however they may be written to only when the device is idle Typically they are written to only once after system power up They are set to default values upon Hardware or Software Reset (Default Wake-Up Mode) The default values are chosen so as to allow the M82510 to be fully software compatible with the IBM PC Async Adapter (INS 8250A 16450) when in the default wakeup mode The M82510 can operate in the High Performance mode by programming the configuration registers as necessary The configuration options available to the user are listed below Table 11 Configuration Options Interrupt Acknowledge Mode Automatic Manual Receive Sampling Window Size Start Bit Detection Mode DPLL Disable Enable mLAN (8051) Address Recognition Manual Semi-Automatic Automatic Diagnostics Loopback Remote Local Echo Yes No Disable Error Echo Disable Control Address Char Echo FIFO RX FIFO Depth RX TX Threshold Clock Options RX TX Clock Mode 1X 16X RX TX Clock Source BRGA BRGB BRGA B Operation Mode Timer BRG BRGA B Divide Count BRGA B Source Sys Clock SCLK Pin BRGA Output (BRGB Only) Control Character Recognition None Standard ASCII EBCDIC Two User Programmed TX Operation RTS CTS Control Manual Semi-Automatic Automatic Parity Mode Stop Bit Length Character Size I O Pins Select Function for Each Multifunction Pin Select Direction for Multifunction Pin (If Applicable)
16
M82510
1 IMD
INTERNAL MODE REGISTER IMD Internal Mode Register
271072 - 14
This register defines the general device mode of operation The bit functions are as follows 7-4 IAM Reserved Interrupt Acknowledge Mode Bit 0 1 Manual acknowledgement of pending interrupts Automatic acknowledgement of pending interrupts (upon CPU service)
ULM
uLAN Mode 0 1 Normal Mode uLAN Mode
This bit enables the M82510 to recognize and or match address using the 9-bit MCS-51 asynchronous protocol LEM Loopback Echo Mode Select
This bit when set configures the M82510 for the automatic acknowledge mode This causes the M82510 INT line to go low for two clock cycles upon service of the interrupt After two clock cycles it is then updated It is useful in the edge triggered mode In manual acknowledgement mode the CPU must explicitly issue a command to clear the INT pin (The INT pin then goes low for a minimum of two clock cycles until another enabled status register bit is set ) RFD Receive FIFO Depth 0 1 Four Bytes One Byte
This bit selects the mode of loopback operation or the mode of echo operation depending upon which operation mode is selected by the Modem Control register bit LC In loopback mode (Modem Control register bit LC e 1) it selects between local and remote loopback 0 1 Local Loopback Remote Loopback
In echo mode (Modem Control register bit LC e 0) it selects between echo or non-echo operation 0 1 No Echo Echo Operation
This bit configures the depth of the Rx FIFO With a FIFO depth of one the FIFO will act as a 1-byte buffer to emulate the 8250A
17
M82510
2 LCR
LINE CONFIGURE REGISTER LCR Line Configure Register
271072 - 15
This register defines the basic configuration of the serial link DLAB Divisor Latch Access Bit This bit when set allows access to the Divisor Count registers BAL BAH BBL BBH registers SBK Set Break Bit This bit will force the TxD pin low The TxD pin will remain low (regardless of all activities) until this bit is reset PM2 PM0 Parity Mode Bits These three bits combine with the SPF bit of the Transmit Mode register to define the various parity modes See Table 12 Table 12 Parity Modes PM0 0 1 1 1 1 1 SPF X 0 0 0 0 1 PM2 X 0 0 1 1 0 PM1 X 0 1 0 1 0 Function No Parity Odd Parity Even Parity High Parity Low Parity Software Parity SBL2 0 0 0 0 1 1 1 1
Table 13 Stop Bit Length SBL1 0 0 1 1 0 0 1 1 SBL0 0 1 0 1 0 1 0 1 Stop Bit Length 16X 1X 44 6 4 or 8 4 34 44 54 64 74 84
1 1 1 1 1 2
6 4 if character length is 5 bits else 8 4
CL0 CL1 Character Length Bits These bits together with the Transmit Mode register bit NBCL define the character length See Table 14 Table 14 Character Length NBCL 0 0 0 0 1 CL1 0 0 1 1 0 CL0 0 1 0 1 0 Character Length 5 BITS 6 BITS 7 BITS 8 BITS 9 BITS
SBLO Stop Bit Length This bit together with SBL1 and SBL2 bits of the Transmit Mode register defines the Stop-bit lengths for transmission The Rx machine can identify 3 4 stop bit or more See Table 13
18
M82510
3 TMD
Transmit Machine Mode Register TMD Transmit Machine Mode Register
271072 - 16
This register together with the Line Configure Register defines the Tx machine mode of operation EED Error Echo Disable Disables Echo of characters received with errors (valid in echo mode only) CED Control Character Echo Disable Disables Echo of characters recognized as control characters (or address characters in uLAN mode) Valid in echo mode only NBCL Nine-Bit Length This bit coupled with LCR (CL0 CL1) selects Transmit Receive character length of nine bits See Table 14 TM1 TM0 Transmit Mode These bits select one of three modes of control over the CTS and RTS lines 00 Manual Mode In this mode the CPU has full control of the Transmit operation The CPU has to explicitly enable disable transmission and activate check the RTS CTS pins
01
Reserved
10 Semi-Automatic Mode In this mode the M82510 transmits only when CTS input is active The M82510 activates the RTS output as long as transmission is enabled 11 Automatic Mode In this mode the M82510 transmits only when CTS input is active The RTS output is activated only when transmission is enabled and there is more data to transmit SPF Software Parity Force This bit defines the parity modes along with the PM0 PM1 and PM2 bits of the LCR register When software parity is enabled the software must determine the parity bit through the TxF register on transmission or check the parity bit in RxF upon reception See Table 12 SBL2 SBL1 Stop Bit Length These bits together with the SBL0 bit of the LCR register define the stop bit length See Table 13
19
M82510
4 FMD FIFO MODE REGISTER FMD FIFO Mode Register
271072 - 17
This register configures the Tx and Rx FIFO's threshold levels the occupancy levels that can cause an interrupt 7 6 Reserved
cated by these bits the Rx FIFO Interrupt is activated 3 2 Reserved
RFT1 RFT0 Receive FIFO Threshold When the Rx FIFO occupancy is greater than the level indi-
TFT1 TFT0 Transmit FIFO Threshold When the TX FIFO occupancy is less than or equal to the level indicated by these bits the Tx FIFO Interrupt is activated
5 ACR0
ADDRESS CONTROL CHARACTER REGISTER 0 ARC0 Address Control Character Register 0
271072 - 18
This register contains a byte which is compared to each received character The exact function depends on the configuration of the IMD register In normal mode this register may be used to program a special control character a matched character will be reported in the RECEIVE STATUS register The maximum length of the control characters is eight bits If the length is less than eight bits then the
character must be right justified and the leading bits be filled with zeros In uLAN mode this register contains the eight-bit station address for recognition In this mode only incoming address characters (i e characters with address bit set) will be compared to these register The PCRF bit in the RECEIVE STATUS register will be set when an Address or Control Character match occurs
6 ACR1
ADDRESS CONTROL CHARACTER REGISTER 1 ARC1 Address Control Character Register 1
271072 - 19
NOTE This register is identical in function to ACR0
20
M82510
7 RMD
RECEIVE MACHINE MODE REGISTER RMD Receive Machine Mode Register
271072 - 20
This register defines the Rx Machine mode of operation uCM0 uCM1 uLAN Control Character Recognition Mode In normal mode it defines the Control Character recognition mode In ulan mode they define modes of address recognition In uLAN mode selects the mode of address recognition 00 Manual Mode Rx Machine reports reception of any address character via CRF bit of RECEIVE STATUS register and writes it to the Rx FIFO 01 Semi-Automatic Mode Operates the same as Manual Mode but in addition the Rx Machine OPENS (unlocks) the Rx FIFO upon reception of any address characters Subsequent received characters will be written into the FIFO (Note it is the user's responsibility to LOCK the FIFO if the address character does not match the station's address ) 10 Automatic Mode The Rx Machine will OPEN (unlock) the Rx FIFO upon Address Match In addition the Rx Machine LOCKs the Rx FIFO upon recognition of address mismatch i e it controls the flow of characters into the Rx FIFO depending upon the results of the address comparison If a match occurs it will allow characters to be sent to the FIFO if a mismatch occurs it will keep the characters out of the FIFO by LOCKING it
11
Reserved
In normal Mode selects the mode of Standard Set Control Character Recognition (programmed control characters are always recognized) 00 01 10 11 No Standard Set Control Characters Recognized ASCII Control Characters (00H 1 FH a 7FH) Reserved EBCDIC Control Character Recognized (00H b 3FH)
DPD Disable Digital Phase Locked Loop When set disables the DPLL machine (Note using the DPLL in a very noisy media may increase the error rate ) SWM Sampling Window Mode the mode of data sampling 0 1 This bit controls
Small Window 3 16 sampling Large Window 7 16 sampling This bit controls
SSM Start Bit Sampling Mode the mode of Start Bit sampling 0 1
Majority Voting for start bit In this mode a majority of the samples determines the bit In this mode if one of the bit samples is not `0' the start bit will not be detected
21
M82510
8 CLCF
CLOCKS CONFIGURE REGISTER CLCF Clocks Configure Register
271072 - 21
This register defines the Transmit and Receive Code modes and sources RxCM Rx Clock Mode This bit selects the mode of the receive clock which is used to sample the received data 0 1 16X Mode 1X Mode In this mode the receive data must be synchronous to the Rx Clock supplied via the SCLK pin
TxCM Transmit Clock Mode This bit selects the mode of the Transmit Data Clock which is used to clock out the Transmit Data 0 1 16X Mode 1X Mode In this mode the Transmit data is synchronous to the Serial Clock supplied via the SCLK pin
RxCS Rx Clock Source This bit selects the source of the internal receive clock in the case of 16X mode (as programmed by the RxCM bit above) 0 1 BRGB Output BRGA Output BRGA CONFIGURATION REGISTER BACF
TxCS Transmit Clock Source Selects the source of internal Transmit Clock in case of 16X mode 0 1 BRGB Output BRGA Output
9 BACF
BRGA Configuration Register
271072 - 22
This register defines the BRGA clock sources and the mode of operation BACS BRGA Clock Source Selects the input clock source for Baud Rate Generator A 0 1 System Clock SCLK Pin
BAM BRGA Mode of Operation Selects between the Timer mode or the Baud Rate Generator Mode 0 1 Timer Mode (in this mode the input clock source is always the system clock) Baud Rate Generator Mode
This bit has no effect if BRGA is configured as a timer
22
M82510
10 BBCF BRGB CONFIGURATION REGISTER BBCF BRGB Configuration Register
271072 - 23
This register defines the BRGB clock sources and mode of operation (Note BRGB can also take its Input Clock from the output of BRGA ) BBCS1 BBCS0 These two bits together define the input Clock Sources for BRGB These bits have no effect when in the timer mode 00 01 System Clock SCLK Pin
10 11 BBM 0 1
BRGA Output Reserved BRGB Mode of Operation Timer Mode (In this mode the input clock source is always the system clock ) BRG Mode
11 BAL
BRGA DIVIDE COUNT LEAST SIGNIFICANT BYTE BAL BRGA Divide Count Low Byte
271072 - 24
This register contains the least significant byte of the BRGA divisor count 12 BAH BRGA DIVIDE COUNT MOST SIGNIFICANT BYTE BAH BRGA Divide Count High Byte
271072 - 25
This register contains the most significant byte of the BRGA divisor count 13 BBL BRGB DIVIDE COUNT LEAST SIGNIFICANT BYTE BBL BRGB Divide Count Low Byte
271072 - 26
This register contains the least significant byte of the BRGB divisor count 23
M82510
14 BBH
BRGB DIVIDE COUNT MOST SIGNIFICANT BYTE BBH BRGB Divide Count High Byte
271072 - 27
This register contains the most significant byte of the BRGB divisor count 15 PMD I O PIN MODE REGISTER PMD I O Pin Mode Register
271072 - 28
This register is used to configure the direction and function of the multifunction pins The following options are available on each pin 1 Direction Input or Output Pin 0 Defines the Pin as an output pin (general purpose or special function) 1 Defines the pin as an input pin 2 Function General purpose or special purpose pin (no effect if the pin is programmed as an Input) 0 1 0 1 special function output pin general purpose output pin DIOD DCD ICLK OUT1 Direction Output ICLK or OUT1 (depending on bit DIOF) Input DCD DIOF DCD ICLK OUT1 Function (output mode only)
0 1
0 1
0 1
0 1 0 1
ICLK (Output of the Internal System Clock) OUT1 general purpose output Controlled by MODEM CONTROL Register DTAD DSR TA OUT0 Direction Output TA or OUT0 (Dependent upon DTAF) Input DSR DTAF DSR TA OUT0 Direction (output mode only) TA (BRGA Output or Timer A Termination Pulse) OUT0 (general purpose output controlled by MODEM CONTROL) RRF RI SCLK Function SCLK (Receive and or Transmit Clock) RI DTF DTR TB Function TB (BRGB Output Clock on Timer B termination pulse depending upon the mode of BRGB) DTR
24
M82510
INTERRUPT STATUS REGISTERS
The M82510 uses a two layer approach to handle interrupt and status generation Device level registers show the status of the major M82510 functional block (MODEM FIFO Tx MACHINE Rx MACHINE TIMERS etc ) Each block may be examined by reading its individual block level registers Also each block has interrupt enable generation logic which may generate a request to the built-in interrupt controller the interrupt requests are then resolved on a priority basis 16 GER GENERAL ENABLE REGISTER GER
Interrupt Masking
The M82510 has a device enable register GER which can be used to enable or mask-out any block interrupt request Some of the blocks (Rx Machine Modem Timer) have an enable register associated with their status register which can be used to mask out the individual sources within the block Interrupts are enabled when programmed high
General Enable Register
271072 - 29
This register enables or disables the bits of the GSR register from being reflected in the GIR register It serves as the device enable register and is used to mask the interrupt requests from any of the M82510 block (See Figure 1) TIE Timers Interrupt Enable TxIE Transmit Machine Interrupt Enable 17 RIE RECEIVE INTERRUPT ENABLE REGISTER RIE
MIE RxIE TFIE RFIE
Modem Interrupt Enable Rx Machine Interrupt Enable Transmit FIFO Interrupt Enable Receive FIFO Interrupt Enable
Receive Interrupt Enable Register
271072 - 30
This register enables interrupts from the Rx Machine It is used to mask out interrupt requests generated by the status bits of the RST register CRE Control uLAN Address Character Recognition Interrupt Enable Enables Interrupt when CRF bit of RST register is set PCRE Programmable Control Address Character Match Interrupt Enable Enables Interrupt on PCRF bit of RST BkTe Break Termination Interrupt Enable
BkDE Break Detection Interrupt Enable able Interrupt on BkD bit of RST FEE Framing Error Enable FE bit of RST PEE Parity Error Enable bit of RST
En-
Enable Interrupt on
Enable Interrupt on PE Enable Interrupt on
OEE Overrun Error Enable OE bit of RST
25
M82510
18 TMIE
TIMER INTERRUPT ENABLE REGISTER TMIE Timers Interrupt Enable Register
271072 - 31
This is the enable register for the Timer Block It is used to mask out interrupt requests generated by the status bits of the TMST register
TBIE Timer B Expired Interrupt Enable Enables Interrupt on TBEx bit of TMST TAIE Timer A Expired Interrupt Enable ables Interrupt on TAEx bit of TMST En-
19 MIE MODEM INTERRUPT ENABLE REGISTER MIE Modem Interrupt Enable Register
271072 - 32
This register enables interrupts from the Modem Block It is used to mask out interrupt requests generated by the status bits of the MODEM STATUS register DCDE Delta DCD Interrupt Enable Enables Interrupt on DDCD bit of MODEM STATUS RIE Delta RI Interrupt Enable on DRI bit of MODEM STATUS Enables Interrupt
CTSE Delta CTS Interrupt Enable Enables Interrupt on DCTS bits of MODEM STATUS
STATUS INTERRUPT
The M82510 has two device status registers which reflect the overall status of the device and five block status registers The two device status registers GSR and GIR and supplementary in function GSR reflects the interrupt status of all blocks whereas GIR depicts the highest priority interrupt only GIR is updated after the GSR register the delay is of approximately two clock cycles
DSRE Delta DSR Interrupt Enable Enables Interrupt on DSR bit of MODEM STATUS
26
M82510
20 GSR
GENERAL STATUS REGISTER GSR General Status Register
271072 - 33
This register reflects all the pending block-level Interrupt requests Each bit in GSR reflects the status of a block and may be individually enabled by GER GER masks-out interrupts from GIR it does not have any effect on the bits in GSR The only way that the bits can be masked out in GSR (i e not appear in GSR) is if they are masked out at the lower level TIR Timers Interrupt Request This bit indicates that one of the timers has expired (See TMST) TxIR Transmit Machine Interrupt Request Indicates that the Transmit Machine is either empty or disabled (Idle) 21 GIR BANK
MIR Modem Interrupt Request This bit if set indicates an interrupt from the Modem Module (As reflected in MODEM STATUS ) RxIR Receive Machine Interrupt Request reflected in RST ) TFIR Transmit FIFO Interrupt Request FIFO occupancy is below or equal to threshold RFIR Receive FIFO Interrupt Request Occupancy is above threshold (As Tx
Rx FIFO
GENERAL INTERRUPT REGISTER BANK REGISTER General Interrupt Register Bank Register
271072 - 34
This register holds the highest priority enabled pending interrupt from GSR In addition it holds a pointer to the current register segment Writing into this register will update only the BANK bits BANK1 BANK0 Bank Pointer Bits These two bits point to the currently accessible register bank The user can read and write to these bits The address of this register is always two within all four register banks BI2 BI1 BI0 Interrupt Bits 0-2 These three bits reflect the highest priority enabled pending interrupt from GSR
101 100 011 010 001 000
Timer Interrupt (highest priority) Tx Machine Interrupt Rx Machine Interrupt Rx FIFO Interrupt Tx FIFO Interrupt Modem Interrupt (lowest priority)
IPN Interrupt Pending This bit is active low It indicates that there is an interrupt pending The interrupt logic asserts the INT pin as soon as this bit goes active (Note the GIR register is continuously updated so that while the user is serving one interrupt source a new interrupt with higher priority may enter GIR and replace the older interrupt )
27
M82510
22 LSR
LINE STATUS REGISTER LSR Line Status Register
271072 - 35
This register holds the status of the serial link It shares five of its bits with the RST register (BkD FE PE OE and RFIR) When this register is read the RST register (BITS 1- 7) and LSR register (BITS 1 - 4) are cleared This register is provided for compatibility with the INS8250A TxSt Transmit Machine Status Bit Same as TxIR bit of GSR register If high it indicates that the Transmit Machine is in Idle State (Note Idle may indicate that the TxM is either empty or disabled TFSt Transmit FIFO Status Same as TFIR bit of GSR It indicates that the Transmit FIFO level is equal to or below the Transmit FIFO Threshold There are two ways to disable the transmit FIFO status from being reflected in GIR 1 Writing a ``0'' to the TFIE bit of the GER register 2 Dynamically by using the Tx FIFO HOLD INTERRUPT logic When the Tx FIFO is in the Hold State no interrupts are generated regardless of the TFIR and TFIE bits The Transmit FIFO enters the Hold State when the CPU reads the GIR register and the source of the interrupt is Tx FIFO To Exit the CPU must drop the
TFIR bit of GSR by writing a character to Tx FIFO or drop TFIE bit of GER (Disable Tx FIFO) Bkd Break Detected See Bkd bit in RST register for full explanation The BkD bit in RST register is the same as this bit FE Framing Error Detected See FE bit in RST register for a full explanation The FE bit in RST register is the same as this bit PE Parity Error Detected See PE bit in RST register for full explanation The PE bit in RST register is the same as this bit OE Overrun Error See OE bit in RST register for full explanation The OE bit in RST register is the same as this bit RFIR Receive FIFO Interrupt Request This bit is identical to RFIR bit of GSR It indicates that the RX FIFO level is above the Rx FIFO Threshold This bit is forced LOW during any READ from the Rx FIFO A zero written to this bit will acknowledge an Rx FIFO interrupt
28
M82510
23 RST
RECEIVE MACHINE STATUS REGISTER RST Receive Machine Status Register
271072 - 36
This register displays the status of the Receive Machine It reports events that have occurred since the RST was cleared This register is cleared when it is read except for BIT0 Rx FIFO interrupt Each bit in this register when set can cause an interrupt Five bits of this register are shared with the LSR register CRF Control Address Character Received When enabled this bit can cause an interrupt if a control character or address character is received In uLAN Mode indicates that an address character has been received In normal Mode indicates that a standard control character (either ASCII or EBCDIC) has been received PCRF Programmed Control Address Character Received This bit when enabled will cause an interrupt when an address or control character match occurs In uLAN Mode indicates that an address character equal to one of the registers ACR0 or ACR1 has been received
In normal Mode indicates that a character which matches the registers ACR0 or ACR1 has been received BkT Break Terminated This bit indicates that a break condition has been terminated BkD Break Detected This bit indicates that a Break Condition has been detected i e RxD input was held low for one character frame plus a stop BIT FE Framing Error This bit indicates that a received character did not have a valid stop bit PE Parity Error Indicates that a received character had a parity error OE Overrun Error Indicates that a received character was lost because the Rx FIFO was full RFIR Receive FIFO Interrupt Request as the RFIR bit of LSR register Same
29
M82510
24 RXF
RECEIVED CHARACTER FLAGS RxF Receive Flags Register
271072 - 37
This register contains additional information about the character in the RXD register It is loaded by the Rx Machine simultaneously with the RXD register ROK Received Character OK This bit indicates that the character in RXD no parity or framing error The parity error is not included in the s w parity mode RxN Received Character Noisy The character in RXD was noisy This bit valid only in 16X sampling mode indicates that the received character had non-identical samples for at least one of its bits RPE Receive Character Parity Error This bit indicates that the RxD character had a Parity Error However in S W Parity mode it holds the received parity bit as is ACR Address Control Character Marker This bit indicates that the character in RXD is either 25 FLR FIFO LEVEL REGISTER FLR
A control Character in normal Mode An Address Character in uLAN Mode RFE Receive Character Framing Error Indicates that no Stop bit was found for the character in RXD NOTE A Framing Error will be generated for the first character of the Break sequence RND Ninth Bit of Received Character The most significant bit of the character in RXD is written into this bit This bit is zero for characters with less than nine bits BKF Break Flag Indicates that the character is part of a ``break'' sequence
FIFO Level Register
271072 - 38
This register holds the current Receive and Transmit FIFO occupancy levels RFL2 RFL1 RFL0 Receive FIFO Level of Occupancy These three bits indicate the level of Occu-
pancy of the Rx FIFO The valid range is zero (000) to four (100) TFL2 TFL1 TFL0 Transmit FIFO Level of Occupancy These three bits indicate the level of occupancy in the transmit FIFO The valid range is zero (000) to four (100)
30
M82510
26 TMST TIMER STATUS REGISTER TMST Timer Status Register
271072 - 39
This register holds the status of the timers Bits TBEx and TAEx generate interrupts which are reflected in bit TIR of GSR Bits GBS and GAS just display the counting status they do not generate interrupts GBS Gate B State This bit does not generate an interrupt It indicates the counting state of the software gate of Timer B as written through the TMCR register 0 counting disabled 1 counting enabled
GAS Gate A State This bit does not generate an interrupt It reflects the state of the software gate of Timer A as written through the TMCR register 0 1 counting disabled counting enabled
TBEx Timer B Expired When Set generates an interrupt through TIR bit of GSR Indicates that Timer B count has expired This bit is set via the terminal count pulse generated by the timer when it terminates counting TAEx Timer A Expired Same as TBEx except it refers to Timer A
27 MSR
MODEM I O PINS REGISTER MSR Modem I O Pins Status Register
271072 - 40
This register holds the status of the Modem input pins (CTS DCD DSR RI) It is the source of interrupts (MSR 0- 3) for the MIR bit of GSR If any of the above inputs change levels the appropriate bit in MODEM STATUS is set Reading MODEM STATUS will clear the status bits DCDC DCD Complement Holds the complement of the DCD input pin if programmed as an input in PMD DRIC Holds the complement of the RI input pin if programmed as an input in PMD
DRI Delta RI Indicates that there was a high-tolow transition on the RI input pin since the register was last read DDSR Delta DSR Indicates that the DSR input pin has changed state since this register was last read DCTS Delta CTS Indicates that the CTS input pin has changed state since this register was last read
COMMAND REGISTERS
DSRC DSR Complement Holds the complement of the DSR input pin if configured as an input in PMD CTSC CTS Complement Holds the complement of the CTS pin DDCD Delta DCD Indicates that the DCD input pin has changed state since this register was last read 31 The command registers are write only they are used to trigger an operation by the device Once the operation is started the register is automatically reset There is a device level register as well as four block command registers It is recommended that only one command be issued during a write cycle
M82510
28 ICM
INTERNAL COMMAND REGISTER ICM Internal Command Register
271072 - 41
This register activates the device's general functions SRST Device Software RESET Causes a total device reset the effect is identical to the hardware reset (except for strapping options) The reset lasts four clocks and puts the device into the Default Wake-up Mode INTA Interrupt Acknowledge This command is an explicit acknowledgement of the M82510's interrupt request It forces the INT pin inactive for two 29 TCM TRANSMIT COMMAND REGISTER TCM
clocks afterwards the INT pin may again go active if other enabled interrupts are pending This command is provided for the Manual Acknowledge mode of the M82510 StC Status Clear Clears the following status registers RST MSR and TMST PDM Power Down This command forces the device into the power-down mode Refer to the functional description for details
Transmit Command Register
271072 - 42
This register controls the operation of the Transmit Machine FTM Flush Transmit Machine Resets the Transmit Machine logic (but not the registers or FIFO) and enables transmission FTF Flush Transmit FIFO Clears the Tx FIFO
TxEN Transmit Enable by the Transmit Machine
Enables Transmission
TxDi Transmit Disable Disables transmission If transmission is occurring when this command is issued the Tx Machine will complete transmission of the current character before disabling transmission
32
M82510
30 RCM
RECEIVE COMMAND REGISTER RCM Receive Command Register
271072 - 43
This register controls the operation of the Rx machine RxE Receive Enable Enables the reception of characters RxDi Receive Disable Disables reception of data on RXD pin FRM Flush Receive Machine Resets the Rx Machine logic (but not registers and FIFOs) enables reception and unlocks the receive FIFO
FRF
Flush Receive FIFO
Clears the Rx FIFO
LRF Locks Rx FIFO Disables the write mechanism of the Rx FIFO so that characters subsequently received are not written to the Rx FIFO but are lost However reception is not disabled and complete status event reporting continues (This command may be used in the uLAN mode to disable loading of characters into the Rx FIFO until an address match is detected ) ORF Open (Unlock) Rx FIFO This command enables or unlocks the write mechanism of the Rx FIFO
31 TMCR
TIMER CONTROL REGISTER TMCR Timer Control Register
271072 - 44
This register controls the operation of the two M82510 timers It has no effect when the timers are configured as baud rate generators TGA and TGB are not reset after command execution TGB Timer-B Gate Timer B operation 1 0 This bit serves as a gate for
1 0
enables counting disables counting
STB Start Timer B This command triggers timer B At terminal count a status bit is set in TMST (TBEx) STA Start Timer A This command triggers timer A At terminal count a status bit is set in TMST (TAEx)
enables counting disables counting This bit serves as a gate for
TGA Timer-A Gate Timer-A operation
33
M82510
32 MCR
MODEM CONTROL REGISTER MCR Modem Control Register
271072 - 45
This register controls the modem output pins With multi-function pins it affects only the pins configured as general purpose output pins All the output pins invert the data i e their output will be the complement of the data written into this register OUT0 OUT0 Output Bit This bit controls the OUT0 pin The output signal is the complement of this bit LCB Loopback Control Bit This bit puts the M82510 into loopback mode The particular type of loopback is selected via the IMD register OUT2 OUT2 Output Bit This bit controls the OUT2 pin The output signal is the complement of this bit 33 TXD TRANSMIT DATA REGISTER TXD
OUT1 OUT1 Output Bit This bit controls the OUT1 pin The output signal is the complement of this bit RTS RTS Output Bit This bit controls the RTS pin The output signal is the complement of this bit DTR DTR Output Bit This bit controls the DTR pin The output signal is the complement of this bit
DATA REGISTERS
The data registers hold data or other information and may be accessed at any time
Transmit Data Register
271072 - 46
This register holds the next data byte to be pushed into the Transmit FIFO For character formats with more than eight bits of data or with additional components (S W Parity Address Marker Bit) the additional data bits should be written into the TxF regis-
ter When a byte is written to this register its contents along with the contents of the TxF register are pushed to the top of the Transmit FIFO This register is write only
34
M82510
34 TXF
TRANSMIT FLAGS REGISTER TxF Transmit Flags Register
271072 - 47
This register holds some additional components of the next character to be pushed into the Tx FIFO The contents of this register are pushed into the Tx FIFO with the Transmit Data register whenever the TxD register is written to by the CPU uLAN uLAN Address Marker Bit This bit is transmitted in uLAN mode as the address marker bit 35 RXD RECEIVE DATA REGISTER RXD
SP Software Parity Bit This bit is transmitted in S W parity mode as the character's parity bit D8 Ninth Bit of Data In nine-bit character length mode this bit is transmitted as the MSB (D8) bit
Receive Data Register
271072 - 48
This register holds the earliest received character in the Rx FIFO The character is right justified and leading bits are zeroed This register is loaded by the
Rx Machine with the first received character Reading the register causes the next register from the Rx FIFO to be loaded into RxD and RxF registers
35
M82510
SPECIFICATIONS
NOTICE This is a production data sheet The specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Case Temperature under Bias Storage Temperature
b 55 C to a 125 C b 65 to a 150 C Voltage on any Pin (w r t VSS) b 0 5V to VCC a 0 5V b 0 5V to a 7V Voltage on VCC Pin (w r t VSS)
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
Power Dissipation
250 mW
Operating Conditions
Symbol TC VCC Description Case Temperature (Instant On) Digital Supply Voltage Min
b 55
Max
a 125
Units C V
4 50
5 50
DC SPECIFICATIONS DC CHARACTERISTICS
Symbol VIL VIH1 VIH2 VOL VOH ILI ILO ICC ISTBY IOHR IOLR CIN CIO CXTAL (Over Specified Operating Conditions) Notes (1) (1) (2) (2) (8) (3) (8) (4) (5) (6) (9) (10) (11) (7) (7) 11 10 10 10 24
g10 g10
Parameter Input Low Voltage Input High Voltage-Cerdip Input High Voltage-LCC Output Low Voltage Output High Voltage Input Leakage Current 3-State Leakage Current Power Supply Current Standby Supply Current RTS DTR Strapping Current RTS DTR Strapping Current Input Capacitance I O Capacitance X1 X2 Load
Min
b0 5
Max 08 VCC a 0 5 VCC a 0 5 0 45
Units V V V V V mA mA mA MHz mA mA mA pF pF pF
24 26
38 500 04
NOTES 1 Does not apply to CLK X1 pin when configured as crystal oscillator input (X1) IOL e 2 mA 2 IOH e b0 4 mA 3 4 0 k VIN k VCC 5 0 45V k VOUT k (VCC b 0 45) 6 VCC e 5 5V VIL e 0 5V (max) VIH e VCC b 0 5V (min) Typical value e 2 5 mA MHz (Not Tested) Ext 1X CLK IOL e IOH e 0 7 Freq e 1 MHz 8 Does not apply to OUT2 X2 pin when configured as crystal oscillator output (X2) 9 Same as 7 but input clock not running 10 Applies only during hardware reset for clock configuration options Strapping current for logic HIGH 11 Applies only during hardware reset for clock configuration Strapping current for logic LOW
36
M82510
AC SPECIFICATIONS
(Over Specified Operating Conditions) Testing Conditions
SYSTEM CLOCK SPECIFICATIONS
Symbol Parameter Min ACTIVE 54 25 25 10 10 40 18 432 MHz (1) (1) 250 (2) Max Notes DIVIDE BY TWO OPTION TCY 2 TCLCH TCHCL TCH1CH2 TCL2CL1 FXTAL CLK Period CLK Low Time CLK High Time CLK Rise Time CLK Fall Time External Crystal Frequency Rating CLK Period CLK Low Tme CLK High Time CLK Rise Time CLK Fall Time
All AC output parameters are under output load
of 20 to 100 pF unless otherwise specified
AC testing inputs are driven at 2 4V for logic `1'
on CERDIP 2 7V on LCC and 0 45V for logic `0' Output timing measurements are made at 1 5V for both a logical `0' and `1'
In the following tables the units are ns unless
otherwise specified System Interface Specification Specification System Clock
DIVIDE BY TWO OPTION TCY TCLCH TCHCL TCH1CH2 TCL2CL1
INACTIVE 108 54 44 250 15 15 (1) (1)
The M82510 system clock is supplied via the CLK pin or generated by an on-chip crystal oscillator The clock is optionally divided by two The CLK parameters are given separately for internal divide-by-two option ACTIVE and INACTIVE The system clock (after division by two if active) must be at least 16X the Tx or Rx baud rate (the faster of the two)
NOTES 1 Rise fall times are measured between 0 8 and 2 0V 2 Tcy in ACTIVE divide by two option is TWICE the input clock period
RESET SPECIFICATION
Symbol TRSHL TTLRSL TRSLTX Reset Width Parameter CLK X1 Configured to CLK Min 8 TCY 6 TCY 0 TCY b 20 Max Notes (1) (2) (2)
RTS DTR LOW Setup to Reset Inactive RTS DTR Low Hold after Reset Inactive
271072 - 49
NOTES 1 In case of CLK X1 configured as X1 1 Ms is required to guarantee crystal oscillator wake-up 2 RTS DTR are internally driven HIGH during RESET active time The pin should be either left OPEN or externally driven LOW during RESET according to the required configuration of the system clock These parameters specify the timing requirements on these pins in case they are externally driven LOW during RESET The maximum spec on TRSLTX requires that the RTS DTR pins not be forced later than TRSLTX maximum
37
M82510
READ CYCLE SPECIFICATIONS
Symbol TRLRH TAVRL TRHAX TRLDV TCIAD TRHDZ Parameter RD Active Width Address CS Setup Time to RD Active Address CS Hold Time after RD Inactive Data Out Valid Delay after RD Active Command Inactive to Active Delay Data Out Float Delay after RD Inactive Tcy a 15 40 Min 2 Tcy a 65 7 0 2 Tcy a 65 (1) Max Notes
NOTE 1 Command refers to either Read or Write signals
271072 - 50
WRITE CYCLE SPECIFICATION
Symbol TWLWH TAVWL TWHAX TDVWH TWHDX Parameter WR Active Width Address CS Setup Time to WR Active Address and CS Hold Time after WR Data in Setup Time to WR Inactive Data in Hold Time after WR Inactive Min 2 Tcy a 15 7 0 90 12 Max Notes
271072 - 51
NOTE Many of the serial interface pins have more than one function sometimes the different functions have different timings In such a case the timing of each function of a pin is given separately
38
M82510
SCLK PIN SPECIFICATION Symbol TXCY TXLXH TXHXL TXH1XH2 TXL2XL1
16x CLOCKING MODE Parameter SCLK Period SCLK Low Time SCLK High Time SCLK Rise Time SCLK Fall Time Min 216 93 93 15 15 (1) (1) Max Notes
NOTE 1 Rise fall times are measured between 0 8V and 2 0V
SCLK PIN SPECIFICATION Symbol TXCY TXLXH TXHXL TXH1XH2 TXL2XL1
1x CLOCK MODE Parameter SCLK Period SCLK Low Time SCLK High Time SCLK Rise Time SCLK Fall Time Min 3500 1650 1650 15 15 (1) (1) Max Notes
NOTE 1 Rise fall times are measured between 0 8V and 2 0V
RXD SPECIFICATION (1x MODE) Symbol TRPW TRPD Parameter RXD Setup Time to SCLK High RXD Hold Time After SCLK High Min 250 250 Max Notes
271072 - 52
TXD SPECIFICATION (1x MODE) Symbol TSCLKTXD Parameter TXD Valid Delay after SCLK Low Min Max 170 Notes
REMOTE LOOPBACK SPECIFICATION Symbol TRXDTXD Parameter TXD Delay after RXD Min Max 170 Notes
39
M82510
Receive Logic Diagram
271072 - 53
Transmit Logic Diagram
271072 - 54
INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080 INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) 696 000 INTEL JAPAN k k Ibaraki-ken Tel 029747-8511
Printed in U S A xxxx 0896 B10M xx xx

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